Performance Enhanced 6-bit Phase Shifter in 65-nm CMOS Technology

This paper proposes the design of an accurate CMOS 6-bit phase shifter in S-Band. This design is based on switched line phase shifter, where the signal flow path is switched between the phase shifting state and the reference state. The higher angles are achieved by HP/LP filter sections, and the lower angles are realized using simple LC filter sections. The RMS phase error of the design is less than 1° and 2° for 6% and 12% normalized bandwidth respectively. The phase coverage is 360° with a resolution of 5.625° as the LSB. The insertion loss is < 14 dB over the band for all states, which are compensated in transmit mode with a novel single-ended Low Noise Amplifier. Also, an excellent noise Figure of less than 2.4 dB over the entire band is achieved. The phase shifter area designed is found to be less than 0.54 mm2 with 65 nm technology.