A 16MHz BW 75dB DR CT Delta Sigma ADC Compensated for More Than One Cycle Excess Loop Delay

An 800MS/s CT Delta Sigma ADC with 16MHz/32MHz bandwidths consumes 47.6mW from 1.8V and occupies 1mm(2) in a 0.18 mu m CMOS process. The DR/SNR/SNDR for the two bandwidths are 75/67/65 dB and 64/57/57 dB respectively. Excess loop delay (ELD) of more than one cycle is compensated using a fast path outside the flash ADC. This and a low latency flash ADC and delay free DAC calibration result in the highest reported sampling rate in this process.