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A 13.3 mW 60 MHz Bandwidth, 76 dB DR 6 GS/s CT Delta Sigma M with Time Interleaved FIR Feedback
Date Issued
2016
Author(s)
Jain, A
Pavan, S
Abstract
We present a wideband single-bit CT Delta Sigma M that uses a 2x time-interleaved quantizer and FIR DAC. Time interleaving reduces power dissipation and regeneration errors of the FIR DAC when compared to a full rate implementation. Fabricated in a low leakage 65nm CMOS, the prototype modulator operates at 6 GS/s and achieves 67.6/76 dB SNDR/DR in a 60 MHz bandwidth while consuming 13.3 mW. The FoM is 56.5 fJ/conv-step.