Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization

A new algorithm and a novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented in this paper. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by scaling up the image input, followed by down scaling and filtering. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes of up to 1024 × 768 pixels at the real time video rate of 30 frames/s. The video scalar is capable of scaling down XGA format to SVGA format as well. The design has been realized by RTL compliant Verilog coding, and fits into a single chip with a gate count utilization of two million gates. For lower resolution pictures, the mapped device can be scaled down. The present FPGA implementation compares favorably with another ASIC implementation. Also, an MPEG-2 codec implementation is presented for use in applications, where the video scalar and codec may be used to reduce transmission bit rate. Transmission of high resolution pictures of XGA format and above, even after effecting compression, demand very high serial channel bandwidth requirement, far exceeding the prescribed maximum by MPEG-2 standards. This can be circumvented by down scaling and then effecting compression before transmission, trading off for a little image quality, as presented in this paper. © 2004 Elsevier B.V. All rights reserved.