Hardware considerations in FFT processors

In this paper some useful techniques have been given which simplify hardware of the complex multipliers, and reduce the memory required to store Fourier coefficients in FFT processors, with particular reference to the cascade organisation. It has been shown that significant saving in hardware results if the multiplications are done in sign-magnitude form while the other processing may be in 1's complement or 2's complement arithmetic. The multiplication in the proposed manner preserves the characteristics of l's complement or 2's complement multiplications, as the case may be. She symmetry in a unit circle has been exploited to reduce the number of coefficients needed to store from N/2 to N/8. When this scheme is adopted, it allows a further saving in memory by 4 bits/complex word. In other words the memory required by a kth stage of an N(=2n)-point cascade FFT processor, with 2b-bits complex words, is reduced from 2n-k × 2b bits to 2n-k-2 x 2(b-2) bits. It has been shown that a 16-point processor does not require any coefficient storage. The coefficients needed by the first stage of the 32-point cascade FFT processor may be generated simply using few gates.