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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication5
  4. TDC: Tagless DRAM cache
 
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TDC: Tagless DRAM cache

Date Issued
07-08-2018
Author(s)
Swamy Saranam, S. R.
Mutyam, Madhu 
Indian Institute of Technology, Madras
DOI
10.1109/ISVLSI.2018.00026
Abstract
Advancements in 3D-stacking technology lead to the usage of stacked DRAM as a last level cache. DRAM caches present multiple design challenges. DRAM cache tag management overhead is one of them because of large area requirement and high access time for look-up. Numerous techniques have been proposed to handle the challenges involved with the DRAM caches. We consider a design choice wherein the tag array storage is removed completely. In this work, we propose a Tagless DRAM Cache (TDC), that completely removes tag array from the DRAM cache and instead, uses the tag-Array of the SRAM last level cache (LLC) along with DRAM cache way indices to locate data in the DRAM cache. Experimental evaluation, considering 4-core configuration, shows that TDC achieves a speedup of 9.97% when compared to baseline. Further, TDC shows greater promise by providing reduction in average power consumption by 11.22% and average SRAM LLC miss penalty by 30.8%.
Volume
2018-July
Subjects
  • DRAM Cache Organizati...

  • Low power

  • Tagless cache

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