Publication:
FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs

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cris.virtual.author-orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtual.author-orcid0000-0001-8063-0026
cris.virtual.author-orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
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cris.virtual.departmentIndian Institute of Technology, Madras
cris.virtual.department#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtualsource.author-orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtualsource.author-orcid987ef1d2-823f-41f2-a467-26ed6c5e17fd
cris.virtualsource.author-orcid#PLACEHOLDER_PARENT_METADATA_VALUE#
cris.virtualsource.department#PLACEHOLDER_PARENT_METADATA_VALUE#
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dc.contributor.authorLakshmy, A. V.
dc.contributor.authorChester Rebeiro
dc.contributor.authorBhunia, Swarup
dc.date.accessioned2023-09-19T13:34:41Z
dc.date.available2023-09-19T13:34:41Z
dc.date.issued01-01-2022
dc.description.abstractPower side-channel attacks are potent security threats that exploit the power consumption patterns of an electronic device to glean sensitive information ranging from secret keys and passwords to web-browsing activity. While pre-Silicon tools promise early detection of side-channel leakage at the design stage, they require several hours of simulation time. In this paper, we present an analytical framework called FORTIFY that estimates the power side-channel vulnerability of digital circuit designs at signal-level granularity, given the RTL or gate-level netlist of the design, at least 100 times faster than contemporary works. We demonstrate the correctness of FORTIFY by comparing it with a recent simulation-based side-channel leakage analysis framework. We also test its scalability by evaluating FORTIFY on an open-source System-on-Chip.
dc.identifier.doi10.1109/ASP-DAC52403.2022.9712551
dc.identifier.scopus2-s2.0-85126143105
dc.identifier.urihttps://apicris.irins.org/handle/IITM2023/21182
dc.relation.ispartofseriesProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
dc.sourceProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
dc.subjectAnalytical model
dc.subjectPower side-channel attacks
dc.subjectPre-Silicon leakage evaluation
dc.titleFORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs
dc.typeConference Proceeding
dspace.entity.typePublication
oaire.citation.endPage665
oaire.citation.startPage660
oaire.citation.volume2022-January
oairecerif.author.affiliation#PLACEHOLDER_PARENT_METADATA_VALUE#
oairecerif.author.affiliationIndian Institute of Technology, Madras
oairecerif.author.affiliation#PLACEHOLDER_PARENT_METADATA_VALUE#
person.affiliation.cityChennai
person.affiliation.cityGainesville
person.affiliation.id60025757
person.affiliation.id60013959
person.affiliation.nameIndian Institute of Technology Madras
person.affiliation.nameUniversity of Florida
person.identifier.scopus-author-id57483551200
person.identifier.scopus-author-id24473134800
person.identifier.scopus-author-id7003286155
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