A Reduced-Area Capacitor-Only Loop Filter with Polarity-Switched G<inf>m</inf>for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs

A technique to reduce the area of a low-noise sub-sampling PLL (SSPLL) is proposed. The resistor in the loop filter is eliminated. The transconductor driven by the phase detector is switched such that its output consists of a positive and negative pulse with the former wider than the latter. A low frequency zero can thus be realized with a substantially smaller capacitor. Transconductor noise is suppressed to acceptable levels by the high phase-detector gain. In applications that require low out-of-band phase noise, the capacitance can be reduced by $25\times $ or more with typical PLL parameters. A prototype SSPLL from 24.4GHz-29.2GHz with a 50MHz reference clock and bandwidth of 1MHz in 65nm LP CMOS process uses a loop filter capacitance of only 5pF. The conventional topology would require 38pF for the same integrated jitter. The in-band phase noise at 1MHz offset ranges from -90 to -95dBc/Hz, and the out-of-band phase noise at 10MHz offset ranges from -117 to -121 dBc/Hz. The jitter integrated from 10kHz to 50MHz is 330-390 fs. It consumes 18.2mW, exhibiting a minimum FoM of 235dB over the frequency range. The SSPLL occupies an area of only 0.14mm2.