Design of Continuous-Time ΔΣ Modulators with Dual Switched-Capacitor Return-to-Zero DACs

Single-bit continuous-time sigma-delta modulators (CTDSMs) are overly sensitive to clock jitter when a non-return-to-zero (NRZ) feedback DAC is used. One way of addressing this problem is to use a DAC with an exponentially decaying pulse shape, realized using a switched capacitor (SC). Existing variants of the SC feedback DAC degrade linearity due to the high peak-to-average ratio of the feedback waveform and severely compromise the alias rejection of the modulator around multiples of the sampling frequency. We introduce the dual switched-capacitor return-to-zero (Dual-SCRZ) DAC, which combines the low clock jitter sensitivity of a switched-capacitor DAC with the low peak-to-average ratio characteristic of NRZ feedback. Further, this DAC preserves the implicit anti-aliasing feature of the CTDSMs around all odd multiples of the sampling frequency. A single-bit CTDSMs that uses the Dual-SCRZ technique and opamp-assistance to improve linearity and reduce jitter sensitivity achieves 91/85.1/83 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at 256 MHz in a 0.18 μm CMOS process, the modulator dissipates 14.8 mW from a 1.8 V supply.