Integrated layout optimized high-g inductors on high-resistivity SOI substrates for RF front-end modules

This paper describes the effect of substrate resistivity on the performance characteristics of on-chip spiral inductors with an emphasis on high-resistivity (HR) silicon-on-insulator (SOI) substrates. The inductor characteristics are modeled using a physics based broadband and scalable compact model. Measurements show improvements up to 25% in quality factor (Q) characteristics of inductors on HR SOI substrate compared to those on a standard low resistivity bulk CMOS substrates. Electro-magnetic simulations demonstrate that similar Q improvement cannot be achieved by further increasing the substrate resistivity or by using patterned ground shield (PGS) beneath the inductor. Moreover, using a PGS is shown to be detrimental to inductor performance with a HR SOI substrate. With no further improvement in inductor Q possile with substrate engineering, minimizing the losses within the spiral through layout optimization becomes indispensable for improved performance. One such technique, that involves tapered spirals is shown to further increase the inductor Q by 20% over and above that is obtained with HR SOI.