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  1. Home
  2. Indian Institute of Technology Madras
  3. Publication10
  4. A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects
 
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A parallel algorithm, architecture and FPGA realization for high speed determination of the complete visibility graph for convex objects

Date Issued
01-02-2006
Author(s)
Priya, T. K.
K Sridharan 
Indian Institute of Technology, Madras
DOI
10.1016/j.micpro.2005.02.002
Abstract
The complete visibility graph is a valuable geometric structure in robot path planning. The literature on constructing the graph has focussed on sequential algorithms and implementations on general-purpose processors. With an increasing need to handle cluttered and/or dynamic environments, a very high speed solution for constructing the graph via custom hardware becomes important. This paper presents a new parallel algorithm for construction of the complete visibility graph of an environment with multiple convex polygonal objects. The algorithm runs in O(n(p+log(n/p))) time for an environment with p objects having a total of n vertices. Results of implementation of the hardware design in Xilinx Virtex FPGA show that the design operates at high speed with low area requirement. In particular, the solution operates at 50 MHz for n close to 100. Further, the design fits on one FPGA device for fairly large input sizes. © 2005 Elsevier B.V. All rights reserved.
Volume
30
Subjects
  • Architecture

  • Complete visibility g...

  • FPGA realization

  • Robot navigation

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