Options
Observable time windows: Verifying high-level synthesis results
Date Issued
01-04-1997
Author(s)
Bergamaschi, Reinaldo A.
Raje, Salil
Abstract
Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.
Volume
14