Construction and test of the first Belle II SVD ladder implementing the origami chip-on-sensor design

Date Issued
29-01-2016
Author(s)
Irmler, C.
Adamczyk, K.
Aihara, H.
Angelini, C.
Aziz, T.
Babu, V.
Bacher, S.
Bahinipati, S.
Barberio, E.
Baroncelli, Ti
Baroncelli, To
Basith, A. K.
Batignani, G.
Bauer, A.
Behera, P. K.
Bergauer, T.
Bettarini, S.
Bhuyan, B.
Bilka, T.
Bosi, F.
Bosisio, L.
Bozek, A.
Buchsteiner, F.
Casarosa, G.
Ceccanti, M.
ÄŒervenkov, D.
Chendvankar, S. R.
Dash, N.
Divekar, S. T.
Doležal, Z.
Dutta, D.
Forti, F.
Friedl, M.
Frühwirth, R.
Hara, K.
Higuchi, T.
Horiguchi, T.
Ishikawa, A.
Jeon, H. B.
Joo, C.
Kandra, J.
Kang, K. H.
Kato, E.
Kawasaki, T.
Kodyš, P.
Kohriki, T.
Koike, S.
Kolwalkar, M. M.
KvasniÄ ka, P.
Lanceri, L.
Lettenbicher, J.
Maki, M.
Mammini, P.
Mayekar, S. N.
Mohanty, G. B.
Mohanty, S.
Morii, T.
Nakamura, K. R.
Natkaniec, Z.
Negishi, K.
Nisar, N. K.
Onuki, Y.
Ostrowicz, W.
Paladino, A.
Paoloni, E.
Park, H.
Pilo, F.
Profeti, A.
Rao, K. K.
Rashevskaia, I.
Rizzo, G.
Rozanska, M.
Sandilya, S.
Sasaki, J.
Sato, N.
Schultschik, S.
Schwanda, C.
Seino, Y.
Shimizu, N.
Stypula, J.
Suzuki, J.
Tanaka, S.
Tanida, K.
Taylor, G. N.
Thalmeier, R.
Thomas, R.
Tsuboyama, T.
Uozumi, S.
Urquijo, P.
Vitale, L.
Volpi, M.
Watanuki, S.
Watson, I. J.
Webb, J.
Wiechczynski, J.
Williams, S.
Würkner, B.
Yamamoto, H.
Yin, H.
Yoshinobu, T.
DOI
Abstract
The Belle II Silicon Vertex Detector comprises four layers of double-sided silicon strip detectors (DSSDs), consisting of ladders with two to five sensors each. All sensors are individually read out by APV25 chips with the Origami chip-on-sensor concept for the central DSSDs of the ladders. The chips sit on flexible circuits that are glued on the top of the sensors. This concept allows a low material budget and an efficient cooling of the chips by a single pipe per ladder. We present the construction of the first SVD ladders and results from precision measurements and electrical tests.
Volume
11
Subjects