Chakravarthy Mathiazhagan

Driver circuits that save global clock and data switching power by 25% or more using LC resonance for energy recovery are shown. A 10x operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance operation is used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2nH range are sufficient. The design is readily scaled from 90nm to 45nm in standard CMOS processes and is robust with 50% variation in component values. The resulting power savings add up to 10's of watts in high performance processors. © 2013 IEEE.

Driver circuits that save switching power by 25 % or more using LC resonance energy recovery are shown for use in clock and data networks. Resonant and other energy savings circuits are shown from global to local leaf cell clocking. A 10× operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2 nH range are sufficient to support this timing. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. The design is readily scaled from 90 to 45 nm in standard CMOS processes and beyond. It is robust with 50 % variation in component values for functionality and skew performance. The resulting power savings add up to 10’s of watts in high performance processors. Skew reductions are achieved without needing to increase the interconnect widths. A 40 % driver active area reduction is also achieved. The scheme is naturally compatible with dynamic logic allowing their increased use at lower power.

On-chip low skew clock distribution driving large load capacitances can consume as much as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To mitigate this, an energy recovering reconfigurable series resonance solution with all the critical support circuitry is described. This LC resonant clock driver on a 22 nm process node saves about 50% driver power (>40% overall) and has 50% less skew than non-resonant driver at 2 GHz, while operating down to 0.2 GHz for dynamic voltage and frequency scaling. Reconfiguring for pulse mode operation enables further power saving, using latches instead of flip-flop banks, for double data rate applications. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared and verified, to enable synthesis of an optimal topology for a given application.

High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred using an inductor during logic evaluation and recovered back for pre-charge, rather than being wasted. Implementation in a standard 90nm CMOS process illustrates feasibility with realistic on-chip inductors. Inductor values below 5nH are sufficient to operate at 1GHz speed driving 1pF of load while consuming less than 1.1mW of power from a 1.8V supply, thus breaking the f.CV2 barrier. The savings are realized over a wider range of frequency and less sensitive to LC variations than previously reported. © 2012 IEEE.

This paper describes a wireless local loop system under development, based on the DECT air interface standard. The key features of DECT, in particular the use of dynamic channel selection, are described. Propogation measurements that indicate the typical spacing of base stations are reported. A WLL-PSTN interconnect architecture is proposed, and simulation results indicating its capacity are presented.

A low-sensitivity temperature-compensated programmable BJT current-mode low-voltage filtering technique is proposed. We introduce a new technique in which the dc gain and the location of the second pole of the integrator are controlled such that the Q-enhancement, due to the second pole, is canceled by the effect of finite dc gain. The technique is suitable for integration and can work with low-value capacitors. By making the filter time constant exactly proportional to reC, good linear tunability is achieved over many decades. The programming current is varied as proportional to absolute temperature (PTAT) to stabilize the time constant reC. © 1999 IEEE.