Nagendra Krishnapura

Negative feedback is introduced using an integrator as the central element by making intuitive connections with the way we sense the difference between desired and actual values and continuously adjust the latter so that it reaches the desired value. In contrast to the traditional use of a memoryless high gain amplifier as the central element, this approach makes it clear right from the beginning that negative feedback circuits take time to respond (have a finite bandwidth), that some excess delay can be tolerated, while larger excess delays lead to ringing and eventually instability, and that negative feedback circuits can be stabilized by slowing them down. Time domain intuition and analysis lead to key conclusions regarding the stability margin of negative feedback circuits. This approach complements the conventional frequency domain approach by serving as an introduction that anticipates the results that are derived by the latter. The presented approach also lends itself better to synthesis of key negative feedback blocks such as opamps and the phase locked loop. © 2012 IEEE.

A technique is proposed for increasing the data rate transmitted through an inductively coupled chip-to-chip link by resetting the channel state variables. This allows the data rate to be increased well beyond what is implied by the channel bandwidth. In the proposed scheme, the two sides of the link are resonated at the highest possible quality factor, maximizing link gain, and minimizing interference. The transmit signal is a binary matched pulse which maximizes the received signal for a given transmitter voltage limit. High-efficiency switching transmitters can be used for this type of signal. The proposed technique can be applied to communication links in which channel state variables are accessible for reset. For increasing the data rate, it is shown that the proposed state-variable reset technique results in a higher signal-to-noise ratio of the received signal and a higher energy efficiency compared to reducing the quality factor to widen the bandwidth, using equalization, or using multi-level signaling. The technique is demonstrated on a chip-to-chip link with coupled 1.5 mm ×1.5 mm planar inductors separated by 0.5 mm in a 0.18 μ m CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.

A wideband, gain enhanced, high frequency, fully differential operational transconductance amplifier (OTA) with enhanced linearity is proposed. The OTA uses a negative conductance to cancel its output parasitic conductance. An automatic, digitally controlled, feedback tuning loop ensures that the parasitic conductance is tracked across corners. High linearity is achieved by voltage biasing the transistors and allowing higher headroom. The OTA uses a common mode feedback (CMFB) loop for common mode stabilization instead of diode connected transistors which enhances the achievable bandwidth. Simulations in a standard 130 nm CMOS process show a dc gain enhancement from 14 dB to 42 dB when negative conductance in incorporated across process voltage and temperature (PVT). The OTA has an unity gain bandwidth of 20 GHz. It has an input referred noise of 1.75 nV/√Hz and has -40dB total harmonic distortion for an input of 330 mVppd.

A driver amplifier suitable for integration with an 18 bit 500 kS/s successive approximation register analog-to-digital converter (ADC) is reported. It accepts single-ended or fully differential inputs. The driver consumes 12.5 mW from a 5 V supply, has a -115 dB (-120 dB) total harmonic distortion for 8 Vppd output at 1 kHz (10 kHz), a 240 ns settling time to 0.01% accuracy for a 2 Vppd output step, and an input-referred noise of 11.1 nV/√Hz. Simulated 18 bit settling time is 900 ns, and σ input-referred offset is 1.2 mV. This is one of the first reported 18 bit CMOS ADC driver amplifiers, and its performance is comparable to that of the state-of-the-art parts in other processes.

Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher 1/f^{3} phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capacitive paths from the drains of the switching transistors are proposed to make the switching transistors inject noise twice in a cycle and reduce the average ISF to nearly zero. The proposed SQVCOs have a phase noise figure of merit(FoM) close to that of a single-phase VCO for a given tank. They also eliminate mode ambiguity usually present in the coupled VCOs. The 2.4 GHz prototypes of two of the proposed SQVCOs in a 0.13 \mu \text{m} CMOS process have 1/f^{3} phase noise corners of 400 and 150 kHz compared to 3 MHz in the conventional SQVCO. At 1 MHz/3 MHz offset, the proposed SQVCOs have measured phase noise(FoM) of -133.5/-145.1 dBc/Hz (188.2/190.2 dB) and -130/-140.2 dBc/Hz (192.5/193.2 dB) whereas the conventional SQVCO has -125.5/-137.6 dBc/Hz (180.3/183 dB). The average measured phase error over five chips is 0.9°.

Feedback DAC errors in a ΔΣ analog to digital converter are determined by measuring the idle channel output and removing the DAC elements one by one. This method requires simple computation, does not add excess loop delay, and requires no reconfiguration of the ΔΣ modulator. The errors so determined can be used to correct the output codes in the digital domain or the DAC elements in the analog domain. This technique is a useful alternative to the popular dynamic element matching at high speeds as excess delay cannot be tolerated and at low oversampling ratios where DEM can result in tones. Simulation results indicate that the correction values can be obtained to an accuracy that is sufficient to reduce noise and distortion to nearly ideal levels. ©2010 IEEE.

An all-pass filter architecture that can be generalized to high orders, and can be realized using active circuits is proposed. Using this, a compact true-time-delay element with a widely tunable delay and a large delay-bandwidth product (DBW) is demonstrated. This is useful for beamforming and equalization in the lower GHz range where the use of LC or transmission line-based solutions to realize large delays is infeasible. Coarse tuning of delay is realized by changing the filter's order while keeping the bandwidth constant and fine tuning is implemented by changing the filter's bandwidth utilizing the delay-bandwidth tradeoff. A test chip fabricated in 0.13 \mu \text{m} CMOS process demonstrates a delay tuning range of 250 ps-1.7-ns, over a bandwidth of 2 GHz, while maintaining a magnitude deviation of ±0.7 dB. The filter achieves a DBW of 3.4 and a delay per unit area of 5.8 \mathrm {ns/mm^{2}}. The filter has a worst case noise figure of 23 dB, and -40 dB intermodulation (IM3) distortion for 37 mVppd inputs. The chip occupies an active area of 0.6 mm2, and dissipates 112 mW-364 mW of power between its minimum and maximum delay settings. Computed radiation pattern with four antennas spaced \mathrm {\lambda -{fmax}}/2 apart shows ±90° beam steering off broadside.

We describe a digital technique for estimating and correcting time constant shifts in continuous-time delta-sigma modulators. The proposed method is based on the principle that the in-band gain and the out-of-band performance of a modulator are related. If the modulator output is denoted as v(n), we show that the variance of p(n) ≡v(n) — v(n — 1) is a good indicator of the modulator RC time constants. An alternative indicator, which is easier to implement in hardware is proposed. Simulation results demonstrating the effectiveness of the proposed techniques are given. © 2007, IEEE. All rights reserved.