Aniruddhan S

A comprehensive top-down system design methodology is presented and supported with a design of a Front-End Module (FEM) for 5G mobile applications targeting 24GHz-29GHz. While adopting package and PCB floor-planning and thermal challenges early in the design, a link budget analysis of a FEM in a system simulator followed by an implementation in GlobalFoundries' 22nm FDSOI process is reported with a focus on novel architectures to address system constraints. The FEM shows an excellent correlation between simulations and measurements and is further characterized post silicon by applying actual 5G signals in a real-time measurement mimicked simulation environment. A unified environment for co-designing and analysing the IC and package system is also described.

In this work, injection locking in switching power amplifiers (PAs) is studied. Traditionally, injection-locked PAs (ILPAs) have supported phase modulation, with injection locking used primarily to improve the power-added efficiency by reducing the power required to drive the ILPA. Since the output power in conventional ILPA architectures is mainly contributed by the locked oscillator in an ILPA, the amplitude modulation is difficult to achieve unless supply modulation is employed. In the ILPA presented in this work, it is shown that by injection locking a switching PA and a power oscillator, improvement in both power-added efficiency and drain efficiency can be achieved as compared to just a switching PA. Moreover, amplitude modulation at a fixed supply voltage is achieved using an RF-DAC approach to scale both the switching PA and the locked oscillator. This approach employs variable injection-strengths varying from ≤1 (weak injection locking) to >1 (strong injection locking) to achieve the required power back-off. Accordingly, new formulations are introduced to extend the existing injection locking theory for injection strengths >1 case in ILPAs. Benefits of a larger injection strength on lock-range, maximum allowable symbol rate, AM-PM distortion and phase noise performance for an ILPA is provided. An ILPA is designed to support 64-QAM and implemented in a standard 65-nm bulk CMOS process. A peak drain efficiency of 42.7% and power-added efficiency of 40% is measured at the highest output power of 23 dBm, operating from a 1.45 V PA power supply at 2.5 GHz. Modulation tests with 5/50 MSym/s 64-QAM signals achieve the measured RMS EVM of 1.9%/3.1% with the average output power, drain efficiency and power-added efficiency of 18.1 dBm, 27.9% and 25.8% at 2.5 GHz, respectively.

Electrical balance-based full-duplex front-end allows high power operation but has strong tradeoff between Tx and Rx insertion loss. In this paper, we present a capacitive bridge-based duplexer for full-duplex operation with tunable Tx/Rx insertion loss to improve link budget in an asymmetric data network. Theoretical analysis is done to show that capacitive bridge-based duplexer can be better than hybrid transformer in CMOS process. Capacitive bridge architecture is suitable for insertion loss tunability and this tunability gives an additional advantage of increasing the range of allowed antenna impedance for the given balance network. The fully integrated duplexer with receiver is implemented in a 130-nm CMOS process, and is capable of handling Tx power of upto +16dBm at antenna. The prototype chip demonstrates tunable Tx/Rx insertion loss achieving an overall receiver noise figure of 5.7-7.5dB and a Tx insertion loss of 3.9-5.6dB. Self-interference cancellation of >50dB is measured for 20-MHz RF bandwidth in 2.4-2.6-GHz frequency range.

An ultra low power low noise analog front-end for ECG signal acquisition is demonstrated. Key to its performance is a multi-frequency chopping technique that helps to significantly reduce power consumption by frequency-division multiplexing of two channels in a single low noise instrumentation amplifier. A complete two-channel analog front-end, chopped at frequencies of 4 kHz and 8 kHz, is implemented in a 0.18 μm CMOS technology from UMC. A current reuse technique is employed in the first stage of the instrumentation amplifier to further improve efficiency. Simulation results show that the front-end achieves an input-referred noise voltage density of 79 nV/√Hz while consuming a current of 460 nA per channel from a 1.2 V power supply. The 1/f noise corner of the system is around 10 Hz and the CMRR of 138 dB.

The concept of electrical balance is used to achieve wideband isolation in an asymmetric 2.4 GHz directional coupler. An intuitive approach using impedance transformation property of transmission lines is used to develop the theory for designing arbitrary-coupling-ratio directional couplers. A coupler based on this theory is designed and fabricated on a two-layered RO4003C PCB. The coupler achieves a return loss of better than 10 dB over a 1.7-2.7 GHz range. The transmission coefficients of the strongly and weakly coupled ports are around-3.5 dB and-5 dB respectively, at 2.4 GHz. The isolation is better than 25 dB over a 1.4-3 GHz range.

An ultra low power low noise analog front-end for ECG signal acquisition is demonstrated. Compared to previously reported work, this front-end promises a significant increase in the Common Mode Rejection Ratio (CMRR) without any compromise in signal quality. Chopper stabilization and current reuse technique is employed in the instrumentation amplifier to further improve efficiency. A common mode feed back loop to minimize interferences is implemented which boosts the CMRR to 139 dB at 50 Hz. A complete single channel analog front-end chopped at 2 kHz is implemented in a TSMC 0.18 μm CMOS technology. Simulation results show that the front-end achieves an input referred noise voltage density of 90 nV √Hz while consuming a current of 350 nA per channel from a 1.5V power supply. The 1/f noise corner of the system is less than 10 Hz.

In this article, we present an efficient signal conditioning scheme for a previously developed planar core-less linear variable differential transformer (LVDT). The stationary coils are excited with variable-amplitude complementary sinusoidal current signals through a Howland source using a closed-loop controller in such a way that the moving coil voltage is maintained close to zero. The ratio of the difference to the sum of the amplitudes of the applied voltages is taken as the output, which is proportional to the moving coil position. The highlight is that any external interference can be detected by monitoring the null voltage, which allows taking remedial measures like switching of operating frequency. Tests on a prototype sensor with this scheme implemented show improvement in positioning performance by more than one order of magnitude under strong interference near the operating frequency. Other benefits include insensitivity to variations in the forward path gain and a better update rate. The new scheme also retains the characteristics of tolerance to vertical displacement, good linearity, and high resolution previously expounded.

This paper presents a simple, novel interfacing scheme for linear variable differential transformer (LVDT) that does not require a precise sine wave oscillator (with stable amplitude and frequency) for excitation or any phase matching circuit like traditional methods. The primary and the secondary coils of the LVDT are integral parts of a relaxation oscillator (RO). The RO injects a current waveform with a triangular shape through the primary coil which in turn induces a square-shaped voltage waveform in the secondary coils. The RO utilizes the amplitudes of those waveforms and generates a pulsewidth modulation (PWM) output signal whose duty cycle ratio is proportional to the measurand, core position. This quasi-digital PWM signal is passed through a low-pass filter to obtain an analog output. PWM time period measurement using a counter yields a digital output. This method guarantees good stability since the output is dependent only on a pair of dc reference voltages apart from the transformation constant of the sensor. A detailed analysis of the sources of error, their effect on the performance of the scheme and appropriate design choices for error mitigation are also presented. A prototype of the proposed circuit was built and tested in the laboratory. The nonlinearity error noted from the tests conducted was less than 0.16% for the analog output and 0.18% for the digital output. A resolution of up to 11 bits was achieved for the digital output.

Two 28GHz mm-wave quadrature voltage-controlled oscillator designs in a 45nm bulk CMOS process are reported in this work. The first topology uses two VCOs coupled with each other using cascode devices. The second topology uses a single VCO followed by a Lange Coupler to give quadrature phase outputs. This comparative study shows that the latter exhibits better phase noise and tuning range with respect to the former. Post-layout EM simulations of the Lange Coupler QVCO predict an improvement of 4-6 dB in phase noise over the Cascode Injected QVCO, across all bit configurations. The total dc power consumption of this Lange coupled QVCO with two buffers is 20 mW when running at a power supply of 1.1V.

An ultra-low-voltage 5 GHz differential low noise amplifier (LNA) is designed and simulated in a UMC 130nm CMOS process. It employs the Darlington structure for improved fT in sub-Threshold region, and operates from a supply voltage of just 0.6V while consuming a total current of 1.4mA. The cascode-less LNA implements capacitive feedback neutralization for improved stability. The LNA exhibits a peak voltage gain of 25dB and minimum noise figure (NF) of 1.8dB. It is input matched to a differential resistance of 100Ω with input reflection coefficient S11 < -10dB over 5.1-5.9 GHz, and the input third-order intercept (IIP3) is +10dBm.