Nitin Chandrachoodan

Microfluidics is an upcoming field of science that is going to be used widely in many safety-critical applicationsincluding healthcare, medical research and defence. Hence, technologies for fault testing and fault diagnosis of these chips areof extreme importance. In this study, the authors propose a scalable pseudo-exhaustive testing and diagnosis methodology forflow-based microfluidic biochips. The proposed approach employs a divide-and-conquer based technique wherein, largearchitectures are split into smaller sub-architectures and each of these are tested and diagnosed independently.

In this paper we describe the design and development of the Command and Data Management System (CDMS) of the nano-satellite of IIT Madras, named IITMSAT. The CDMS module uses a 32-bit ARM microcontroller from Freescale - KL46Z256VLL4. This module is responsible for decoding the telecommands sent from the ground station, and transmits the time-stamped payload data back as telemetry packets. The SD card on the CDMS board stores the satellite's health and science data as and when it is acquired in the orbit. The data is transmitted to the ground station (GS) during the satellite's visibility period. The interface board (I/F) links the Flight Computer module and CDMS board along with other electronics onboard. Throughout the design phase, the cost was kept as low as possible, without compromising on performance of the system. Custom-designed protocol and data frame format for communication between the satellite and ground station was completely developed from scratch, based on CCSDS cubesat standards.

We demonstrate the use of a Time-Multiplexed Opto-Electronic Oscillator based Coherent Ising Machine(CIM) to solve Maxcut Problems. Time multiplexing helps reduce system complexity and size, with good scaling against problem size. Benchmarks against state-of-the-art classical solvers show comparable performance, with encouraging results for further improvements.

HTTP/2 introduced multi-threaded server operation for performance improvement over HTTP/1.1. Recent works have discovered that multi-threaded operation results in multiplexed object transmission, that can also have an unanticipated positive effect on TLS/SSL privacy. In fact, these works go on to design privacy schemes that rely heavily on multiplexing to obfuscate the sizes of the objects based on which the attackers inferred sensitive information. Orthogonal to these works, we examine if the privacy offered by such schemes work in practice. In this work, we show that it is possible for a network adversary with modest capabilities to completely break the privacy offered by the schemes that leverage HTTP/2 multiplexing. Our adversary works based on the following intuition: restricting only one HTTP/2 object to be in the server queue at any point of time will eliminate multiplexing of that object and any privacy benefit thereof. In our scheme, we begin by studying if (1) packet delays, (2) network jitter, (3) bandwidth limitation, and (4) targeted packet drops have an impact on the number of HTTP/2 objects processed by the server at an instant of time. Based on these insights, we design our adversary that forces the server to serialize object transmissions, thereby completing the attack. Our adversary was able to break the privacy of a real-world HTTP/2 website 90% of the time, the code for which will be released. To the best of our knowledge, this is the first privacy attack on HTTP/2.

We present a Graphics Processing Unit (GPU) implementation of a Belief Propagation (BP) based decoder for polar codes. The BP decoding algorithm is implemented to utilize the parallel computing capability of the GPUs. We show how the algorithm can make use of parallelism both at the thread level and block level, and by utilizing the limited shared memory available on GPUs, a real time decoding performance is achieved. The resulting algorithm is able to achieve a decoding throughput of almost 5Mbps while maintaining a frame error rate below 10-3 on code blocks of 1024 bits. © 2012 IEEE.

Approximate circuit design has gained significance in recent years targeting error-tolerant applications. In the literature, there have been several attempts at optimizing the number of approximate bits of each approximate adder in a system for a given accuracy constraint. For computational efficiency, the error models used in these routines are simple expressions obtained using regression or by assuming inputs or the error is uniformly distributed. In this article, we first demonstrate that for many approximate adders, these assumptions lead to an inaccurate prediction of error statistics for multi-level circuits. We show that mean error and mean square error can be computed accurately if static probabilities of adders at all stages are taken into account. Therefore, in a system with a certain type of approximate adder, any optimization framework needs to take into account not just the functionality of the adder but also its position in the circuit, functionality of its parents, and the number of approximate bits in the parent blocks. We propose a method to derive parameterized error models for various types of approximate adders. We incorporate these models within an optimization framework and demonstrate that the noise power is computed accurately.

Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can. be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Runtime programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation. © 2008 IEEE.

In this paper, we propose an algorithm to classify spurious transitions in the activity of a digital circuit as generated and propagated glitches during logic simulation. Using the activities obtained, we compute a criticality metric to identify the nets where glitch minimization techniques are likely to provide the maximum benefit. The proposed metric provides insight into which techniques are best suited for use in glitch reduction for a given circuit. This enables targeted application of glitch reduction techniques. Experiments with several glitch intensive benchmarks show a faster convergence within fewer iterations to solutions with reduced glitch activity. We validate this observation by using the proposed metric to guide the application of some glitch reduction techniques and quantify the resultant savings. The proposed algorithm can be seamlessly incorporated in modern event-driven logic simulators.