Now showing 1 - 10 of 100
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    An Unequal Split Dual Three-Phase PMSM with Extended Torque-Speed Characteristics for Automotive Application
    (01-10-2022)
    Nair, Sandeep V.
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    Layek, Kunal
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    High gradability and wide operating speed range are critical requirements for heavy-duty trucks and off-road electric vehicles. The motor power rating used for such applications can be reduced by selecting a motor with a wide constant power speed range (CPSR). However, permanent magnet synchronous motors (PMSMs) with wide CPSR have limited overloading capability. The operating speed range, as well as the overloading capability, can be improved by increasing the base speed of a low CPSR three-phase PMSM, which results in overdesign. Further, using multigear transmission to achieve a wide operating speed range with a low power motor increases system weight, drivetrain complexity, and maintenance requirement. This article proposes a dual three-phase interior PMSM with an unequal split winding configuration and zero degree winding displacement (uneq0-PMSM) to extend the constant power region and improve the overloading capability without any machine overdesign. The winding split ratio for the proposed configuration is decided to achieve the desired torque-speed characteristic shape for a given requirement. Further, a transition algorithm for smooth changeover between two-winding operation during low-speed and one-winding operation for high-speed is also proposed. The proposed concepts are experimentally validated on a 1.5-kW uneq0-PMSM with 1:3 winding split ratio.
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    A Si IGBT and SiC MOSFET Hybrid Shunt Active Filter
    (02-07-2018)
    Mohapatra, Aloka
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    Bhawal, Shekhar
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    This paper proposes an energy efficient, cost competitive hybrid Shunt Active Filter (SAF) topology with superior current harmonic rejection capability compared to Si IGBT based SAF solutions. Generally, Si IGBT based shunt active filter designs face a serious challenge for higher order harmonic mitigations due to its restricted switching frequency of operation (typically limited to 10 kHz). In this paper, a hybrid shunt active filter (HSAF) solution is proposed where one Si IGBT based inverter eliminates lower order harmonics (5 {th} and 7 {th}) and a SiC MOSFET based inverter draws all higher order harmonics (11 {th}, 13 {th}, The Si IGBT is rated for around 90% of the total load kVA rating but it is switched at 5 kHz switching frequency. On the other hand, SiC MOSFET based inverter is much smaller (nearly 15%) in size but it is switched at 30 kHz to eliminate the higher order harmonics more efficiently. The proposed topology is verified by simulation and experimental results.
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    Publication
    Control technique for 15 kV SiC IGBT based active front end converter of a 13.8 kV grid tied 100 kVA transformerless intelligent power substation
    (31-12-2013)
    Madhusoodhanan, Sachin
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    Bhattacharya, Subhashish
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    This paper discusses the control technique adopted for a 3-Level Neutral Point Clamped (3L-NPC) converter, which is the rectifier stage of a 100 kVA solid state transformer known as the Transformerless Intelligent Power Substation (TIPS) interfacing with 13.8 kV grid. Due to high voltage (13.8 kV) and low power (100 kVA) specification for the rectifier, the control technique needs to be specially designed to control very low magnitude of line current (4.184 A r.m.s). Due to dead time in the converter and harmonic voltage present in the grid, the rectifier current is rich in lower order harmonics (6m±1). Moreover due to very high grid voltage, limiting starting inrush current within the converter current rating is a serious issue. A unified control technique is discussed to mitigate the above mentioned problems. Also the proposed control technique addresses the grid voltage unbalance and d.c bus mid-point voltage unbalance issue faced by the rectifier stage of TIPS. Simulation and SiC IGBT prototype experimental results verify the proposed techniques. © 2013 IEEE.
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    A drain current based short circuit protection technique for SiC MOSFET
    (11-06-2018)
    Sukhatme, Yash
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    Vamshi Krishna, M.
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    Ganesan, P.
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    SiC MOSFETs based power converters are an attractive alternative to IGBTs due to the reduced size and weight of the converter. However, as the leakage inductance is very small it causes a rapid rise in device current under short circuit conditions. As a result, SiC MOSFET cannot withstand short circuit faults for durations as long as the IGBT, thus, the reliability of SiC MOSFET can be a hindrance to it's widespread adoption. This paper analyzes the shortcomings of the present short circuit protection techniques which are presented in literature. Further, a practical short circuit protection technique for SiC MOSFETs by sensing the drain current id from the device di/dt has been presented in the paper. The proposed method eliminates the delays in the present short circuit protection methods and can detect Hard Switching Fault (HSF) and Fault Under Load (FUL) as well.
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    Understanding dv/dt of 15 kV SiC N-IGBT and its control using active gate driver
    (11-11-2014)
    Kadavelugu, Arun
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    Bhattacharya, Subhashish
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    Leslie, Scott
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    Ryu, Sei Hyung
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    Grider, David
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    The ultrahigh voltage (> 12 kV) SiC IGBTs are promising power semiconductor devices for medium voltage power conversion due to feasibility of simple two-level topologies, reduced component count and extremely high efficiency. However, the current devices generate high dv/dt during switching transitions because of the deep punch-through design. This paper investigates the behavior of dv/dt during the two-slope (different slopes before and after punch-through) turn-on and turn-off voltage transitions of these devices, by varying the device current, temperature and field-stop buffer layer design. It is shown that the dv/dt can be minimized by increasing the gate resistance, by taking the turn-on transition as reference. However, it is found that the increase in gate resistance has very weak impact on dv/dt above the punch-through voltage, and also resulting in significantly increased switching energy loss. It is shown that this problem can be addressed by using a two-stage active gate driver, where the gate current is appropriately controlled to limit the dv/dt over punch-through voltage and to minimize the switching energy loss under the punch-through voltage. Experimental results on 15 kV SiC N-IGBTs with field-stop buffer layer thickness of 2 μm and 5 μm are presented up to 11 kV with a detailed discussion of the results.
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    Medium voltage power converter design and demonstration using 15 kV SiC N-IGBTs
    (08-05-2015)
    Kadavelugu, Arun
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    Mainali, Krishna
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    Patel, Dhaval
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    Madhusoodhanan, Sachin
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    Tripathi, Awneesh
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    Bhattacharya, Subhashish
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    Ryu, Sei Hyung
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    Grider, David
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    Leslie, Scott
    This paper summarizes the different steps that have been undertaken to design medium voltage power converters using the state-of-the-art 15 kV SiC N-IGBTs. The 11 kV switching characterization results, 11 kV high dv/dt gate driver validation, and the heat-run test results of the SiC IGBT at 10 kV, 550 W/cm2 (active area) have been recently reported as individual topics. In this paper, it is attempted to link all these individual topics and present them as a complete subject from the double pulse tests to the converter design, for evaluating these novel high voltage power semiconductor devices. In addition, the demonstration results of two-level H-Bridge and three-level NPC converters, both at 10 kV dc input, are being presented for the first-time. Lastly, the performance of two-chip IGBT modules for increased current capability and demonstration of three-level poles, built using these modules, at 10 kV dc input with sine-PWM and square-PWM modulation for rectifier and dc-dc stages of a three-phase solid state transformer are presented.
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    Quick and seamless transition method for I-f to sensorless vector control changeover and on-the-fly start of PMSM drives
    (01-11-2020)
    Nair, Sandeep V.
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    Durga Prasad, N. V.P.R.
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    Kishore Reddy, D.
    A smooth changeover from the I-f method to closed-loop sensorless vector control is a critical requirement for permanent magnet synchronous motor (PMSM) drives using a back-emf based sensorless algorithm for medium- to high-speed range control. The existing methods provide a smooth transition by aligning the angle generated by I-f control to the sensorless estimated angle. However, the overall start-up time increases due to the additional transition interval, which limits the usability of these methods for applications requiring a quick start-up. Furthermore, the use of a direct transition method to reduce the changeover time results in speed and current oscillation if the estimated position using sensorless algorithm is having an error. In the proposed method, the inverter pulses are disabled for a short duration and the machine back-emf is measured after the stator current falls to zero. Therefore, a quick and seamless transition is achieved in the proposed method by accurately estimating the rotor position from the sensed back-emf. The proposed method is also extended to perform on-the-fly start for power failure ride through during short time power supply interruption. The performance of the proposed method is verified using simulation and experiment on a 25 kW PMSM drive.
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    Selection Procedure of Resonant Tank Parameters for an SiC MOSFET based DC/DC Series Resonant Converter
    (02-07-2018)
    Chakraborty, Surja Sekhar
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    Patnala, Saranya
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    Bhawal, Shekhar
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    A systematic approach to select the resonant tank parameters for a DC/DC Series Resonant Converter (SRC) is proposed in this paper. The drawbacks of using sinusoidal approximation model, while selecting those parameters, are also discussed in this paper. Quality factor of the system is derived from an equivalent circuit to get an insight about the harmonics present in the tank current, for a different combination of L and C values. The presence of harmonic components in tank current deteriorates the performance of SRC by increasing conduction and switching losses. A detailed investigation is carried out in this paper to find the factors, responsible for the harmonics in the tank current, through theoretical analysis and simulation studies. Besides, voltage drop across the series capacitor plays a critical role in this selection process, which is also included in this paper. A laboratory prototype of 2kW, 45kHz SiC MOSFET based SRC is built to verify and validate the proposed method.
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    A unified control scheme for harmonic elimination in the front end converter of a 13.8 kV, 100 kVA transformerless intelligent power substation grid tied with LCL filter
    (01-01-2014)
    Madhusoodhanan, Sachin
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    Bhattacharya, Subhashish
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    This paper proposes a simple control scheme to eliminate the lower order harmonics in the line currents of the Front End Converter (FEC) of a 100 kVA Transformerless Intelligent Power Substation (TIPS) connected to the medium voltage (13.8 kV) grid through an LCL filter. Due to medium voltage (13.8 kV) and low power (100 kVA) specification for the FEC, the control technique needs to be specially designed to control very low magnitude of line current (4.2 A rms). Lower order harmonics are present in the grid current due to dead time in the FEC and grid voltage harmonics. Low switching frequency along with the medium voltage and low power levels results in a filter capacitor value that offers low impedance to the lower order harmonic currents. This lower order harmonic current flow through the filter capacitor limits the power that can be delivered by the converter due to lower current rating of the FEC. It also pollutes the control loop and affect system stability. This paper proposes a simple unified control scheme with harmonic current elimination under such conditions. The control scheme eliminates these harmonics in the grid current by regulating the harmonics in the filter capacitor voltage and inductor currents, both on grid side and converter side. System modeling, simulation and experimental results validate the proposed control scheme. © 2014 IEEE.
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    Design Considerations of a 15-kV SiC IGBT-Based Medium-Voltage High-Frequency Isolated DC-DC Converter
    (01-07-2015)
    Tripathi, Awneesh K.
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    Mainali, Krishna
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    Patel, Dhaval C.
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    Kadavelugu, Arun
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    Hazra, Samir
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    Bhattacharya, Subhashish
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    A dual active bridge (DAB) is a zero-voltage switching (ZVS) high-power isolated dc-dc converter. The development of a 15-kV SiC insulated-gate bipolar transistor switching device has enabled a noncascaded medium voltage (MV) isolated dc-dc DAB converter. It offers simple control compared to a cascaded topology. However, a compact-size high frequency (HF) DAB transformer has significant parasitic capacitances for such voltage. Under high voltage and high dV/dT switching, the parasitics cause electromagnetic interference and switching loss. They also pose additional challenges for ZVS. The device capacitance and slowing of dV/dT play a major role in deadtime selection. Both the deadtime and transformer parasitics affect the ZVS operation of the DAB. Thus, for the MV-DAB design, the switching characteristics of the devices and MV HF transformer parasitics have to be closely coupled. For the ZVS mode, the current vector needs to be between converter voltage vectors with a certain phase angle defined by deadtime, parasitics, and desired converter duty ratio. This paper addresses the practical design challenges for an MV-DAB application.