Bhaswar Chakrabarti

Metal-oxide-based resistive random access memory (RRAM) synaptic devices typically suffer from high variability and strongly nonlinear conductance change. In this work, we demonstrate a SiO $_\textit{x}$ -based synapse with low operating voltages, excellent uniformity in the switching operation, and analog tunability of conductance. The devices also exhibit linear and symmetric conductance update. We demonstrate that the enhanced uniformity and analog tunability can be attributed to an interfacial switching mechanism which can be controlled through careful optimization of the device operating conditions.

Two-dimensional (2D) materials and their hetero structures are promising for memristive applications due to their extreme scalability and high performance.1 Threshold switching in 2D-Transition Metal Dichalcogenide (TMDC) memristors has been previously identified for neuromorphic applications.2 On the other hand, accurate control of defect concentration in 2D-TMDC films is necessary for optimized performance of the memristive devices. In this work, we explore a chemical route to control defect concentration in 2D-MoS2 films. We demonstrate that the defect concentration in 2D-MoS2 can be tuned by H2O2 treatment. We then optimize the resistance switching behavior of Au/MoS2/Ag/Au memristors to obtain reliable threshold resistance switching with high on/ off ratio, low operating voltages and self-compliance behavior. This work offers promise for a low-cost, scalable approach to develop 2D-TMDC based high-performance neuromorphic hardware.

Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck. At its heart is a cross-bar architecture with nodal non-volatile-memory elements that performs an analog multiply-and-accumulate operation, enabling the matrix-vector-multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system-level characteristics and chip performance, including speed, power, and classification accuracy. With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non-volatile memory materials will need to demonstrate for a successful CIM technology.

The metal-to-insulator phase transition (MIT) in low-dimensional materials and particularly two-dimensional layered semiconductors is exciting to explore due to the fact that it challenges the prediction that a two-dimensional system must be insulating at low temperatures. Thus, the exploration of MITs in 2D layered semiconductors expands the understanding of the underlying physics. Here we report the MIT of a few-layered MoSe2 field effect transistor under a gate bias (electric field) applied perpendicular to the MoSe2 layers. With low applied gate voltage, the conductivity as a function of temperature from 150 K to 4 K shows typical semiconducting to insulating character. Above a critical applied gate voltage, Vc, the conductivity becomes metallic (i.e., the conductivity increases continuously as a function of decreasing temperature). Evidence of a metallic state was observed using an applied gate voltage or, equivalently, increasing the density of charge carriers within the 2D channel. We analyzed the nature of the phase transition using percolation theory, where conductivity scales with the density of charge carriers as σ ∝ (n − nc)δ. The critical exponent for a percolative phase transition, δ(T), has values ranging from 1.34 (at T = 150 K) to 2 (T = 20 K), which is close to the theoretical value of 1.33 for percolation to occur. Thus we conclude that the MIT in few-layered MoSe2 is driven by charge carrier percolation. Furthermore, the conductivity does not scale with temperature, which is a hallmark of a quantum critical phase transition.

Development of scalable, low-power resistive memory devices (ReRAM) can be crucial for energy efficient neural networks with enhanced compute-in-memory capability. Recent demonstrations show promise for graphene as an electrode material for ultra-low power switching in ReRAMs. However, a limited amount of research has been carried out towards developing a SPICE-based compact model that captures the switching dynamics of such devices. In this work, we investigate a low-power, forming-free resistive memory device with graphene electrodes and a multi-layered TiOx/Al2O3/TiO2 dielectric stack. We first develop a compact model to demonstrate that the switching dynamics can be simulated by considering permanent conductive filaments in the TiOx and TiO2 layers and by the modulation of a tunnelling gap within the Al2O3 layer. The developed devices also exhibit strong rectification behavior in the ON state. We incorporate this rectification behavior in the developed compact model. We also demonstrate that multiple filaments govern the switching dynamics at higher operating current values. The developed model also accurately captures the stochastic variability experimentally observed in the ReRAM devices. This work shows promise for simulation of large-scale networks of graphene-based low-power ReRAM technology.

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

In this paper, we present a physics-based compact model of thermal resistance in Resistive Random-Access Memory (RRAM) devices considering (a) thermal properties of electrode materials, (b) temperature-induced variations in material thermal conductivity, and (c) parasitic heat losses through the oxide surrounding the filament. Fully coupled numerical simulation data obtained from the self-consistent solution of the drift-diffusion equation (for vacancy migration), carrier continuity equation (for electronic conduction), and the Fourier heat diffusion equation (accounting for electro-thermal heating) has been used for developing and validating the proposed model. Excellent agreement is observed between the model and the numerical simulation results. The proposed model is validated with experimentally measured conductive filament temperature obtained from two different temperature sensing methods. Finally, we present a modeling framework to estimate the potential thermal-cross talk in RRAM crossbar arrays. Our results illustrate that a power-dependent thermal resistance model significantly improves the accuracy in estimating the electro-thermal effects in RRAMs.

Understanding the resistance switching behavior of oxide-based memristive devices is critical for evaluating their usefulness in nonvolatile memory and/or in artificial neural networks. Oxide memristors often employ bi- or multilayered metal oxide thin films for improved performance compared to devices with a single-metal-oxide active layer. However, a clear understanding of the mechanisms that lead to improved performance for specific combinations of oxide thin films is still missing. Herein, we fabricated two types of bilayered heterostructure devices, with HfOx/AlOy and AlOy/HfOx bilayer films sandwiched between Au electrodes. Electrical responses of these bilayer devices reveal a digital set and an analog reset transition process. Single-layer HfOx and AlOy devices are also examined as control samples to validate the switching mechanism. The role of bilayered heterostructures is investigated using both the experimental and simulated results. Our results suggest that synergistic switching performance can be achieved with a proper combination of these materials, optimized structures, and proper test conditions. These results open the avenue for designing more efficient double- or multilayered memristive devices for an analog response.

Indium gallium zinc oxide (IGZO)-based ferroelectric thin-film transistors (FeTFTs) are being vigorously investigated for being deployed in computing-in-memory (CIM) applications. Content-addressable memories (CAMs) are the quintessential example of CIM, which conduct a parallel search over a queue or stack to obtain the matched entries for a given input data. CAM cells offer the ability for massively parallel searches in a single clock cycle throughout an entire CAM array for the input query, thereby enabling pattern matching and searching functionality. Therefore, CAM cells are used extensively for pattern matching or search operations in data-centric computing. This paper investigates the impact of retention degradation on IGZO-based FeTFT on the multibit operation in content CAM cell applications. We propose a scalable multibit 1FeTFT-1T-based CAM cell composed of only one FeTFT and one transistor, thus significantly improving the density and energy efficiency compared with conventional complementary metal-oxide-semiconductor (CMOS)-based CAM. We successfully demonstrate the operations of our proposed CAM with storage and search by exploiting the multilevel states of the experimentally calibrated IGZO-based FeTFT devices. We also investigate the impact of retention degradation on the search operation. Our proposed IGZO-based 3-bit and 2-bit CAM cell shows 104 s and 106 s retention, respectively. The single-bit CAM cell shows lifelong (10 years) retention.

In this study, we explore the prevalence of Row Hammer attacks in FeFET-based memory systems. We introduce an analytical model derived from measured data to predict the drift in the programmed threshold voltage state under a given electrical pulse excitation. The results of our research present an efficient means of evaluating the security of FeFET-based memory systems and offer practical guidelines for their optimization.