A parameterized cell design for high-Q, variable width and spacing spiral inductors
The on-chip planar spiral inductors having variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q). In this paper, we present an efficient parameterized cell (pcell) design in cadence using SKILL scripts for automatic layout generation of these complex, high-Q, variable W&S spiral inductors comprising of single ended and symmetric structures with rectangular, hexagonal, octagonal and circular spirals. Electromagnetic simulations are performed on the inductor layouts generated using the developed pcells. The constant W&S and variable W&S spiral inductor structures are fabricated in a 0.18 μm silicon on insulator process. Measurements show ∼25% improvement in the quality factor of variable W%S spiral inductors compared to their constant W&S counterparts and also validates the proper operation of the developed inductor parameterized cells. The presented variable W&S inductor pcell significantly reduces the layout design time of RF circuit designers and also helps in the design automation of these complex inductor structures to boost their own performance and the RF circuits as well.
Series stacked multipath inductor with high self resonant frequency
In this brief, a novel combination of multilayer up-down series stacking and multipath architecture for equal path length is explored for the first time to improve the performance of on-chip inductors. The up-down series winding reduces the interlayer capacitance, thereby increasing both the peak quality-factor (Q) frequency (Q) and self resonant frequency (SRF). The crossover interconnection architecture ensures equal path length at every pair of spiral turns in the series stack. This architecture lowers skin and proximity effect losses in the spiral, increasing the slope of Q characteristics. Thus, using the proposed architecture, both the ac resistance and capacitance are simultaneously reduced while realizing higher inductance values. Implemented in a 0.18μ high resistivity silicon-on-insulator technology using a dual thick metal stack, the proposed inductor achieves more than 10% improvement in peak-Q value, 50% improvement in f Qmax, and 100% improvement in SRF values when compared with a conventional series stacked multipath inductor.
High efficiency millimeter-wave stacked two turn transformer using only top two thick metals
A new high efficiency stacked millimeter-wave transformer is designed and fabricated in 0.18 μm CMOS technology using dual thick metal stack. The proposed configuration allows efficient implementation of two turn stacked transformers, exclusively using top two thick metal layers. Measurements show significant improvements in efficiency, coupling coefficient and current handling when compared to existing two turn stacked transformer configurations. Using the top thick metals substantially increases the current handling while reducing the capacitance to substrate. Further, the proposed transformer exhibits perfect symmetry across both primary and secondary and can be readily converted to a balun.
60 GHz millimeter-wave compact TFMS bandstop filter using transversal resonator in 0.18μm CMOS technology
This study presents the implementation of a millimeter-wave compact bandstop filter (BSF) using the standard 0.18 μm CMOS process. The topology is based on transversal signal interference technique, obtained by connecting two transmission lines with proper characteristic impedances and electrical lengths in parallel. Sharp-rejection characteristics are obtained without using any extra resonators. Moreover, BSF having single-characteristic impedance is analyzed for design simplicity. A compact thin film microstrip structure with meandered signal line is properly constructed without any post processing steps. The overall filter occupies a compact circuit area of less than 0.25 λg × 0.25 λg and exhibits a 20 dB stopband fractional bandwidth of 21% and high-rejection of about-38 dB at centre frequency of 60 GHz. A good agreement between the predicted and measured results is observed up to 110 GHz.
Modeling of High-Q Conical Inductors and MOM Capacitors for Millimeter- Wave Applications
Conical inductors and metal-oxide-metal (MOM) capacitors are shown to have higher quality factor ( ${Q}$ ) characteristics at millimeter wave (mm-wave) frequencies over conventional inductors and nitride MIM capacitors. In this work, Physics-based analytical models are developed for conical inductors and MOM capacitors usable at mm-wave frequencies. The linear voltage profile along the turns of the conical inductor is taken into account for capacitance calculation which is critical in accurately predicting ${Q}$ -values. Two RL networks coupled by capacitors are proposed to capture the frequency-dependent characteristics of the MOM capacitor. The lumped elements in both these device models are frequency independent and can be calculated using layout and process parameters. The proposed models for conical inductors and MOM capacitors are verified with electromagnetic (EM) simulations till 100 GHz. A prototype 60-GHz bandpass filter (BPF) is fabricated using $0.18~\mu \text{m}$ RF-silicon on insulator (SOI) technology to validate the accuracy of the developed compact models. BPF simulation results using the proposed models are shown to be in excellent agreement with those produced with EM simulations and silicon measurements.
Miniaturized millimeter-wave narrow bandpass filter in 0.18 μm CMOS technology using spiral inductors and inter digital capacitors
In this paper, first, we demonstrate that millimeter wave bandpass filters at 60 GHz can be realized using miniaturized lumped capacitors and spiral inductors instead of traditional microstrip transmission line structures. Second, at these frequencies, inter digital capacitors are shown to have a much higher quality factor (Q) than high density metal- insulator-metal (MIM) capacitors. All the circuit elements are layout optimized using electro-magnetic tools which resulted in Qs ≥ 15 over the frequency band of operation. The filter is fabricated in 0.18 μm high resistivity RF silicon on insulator CMOS technology with a top thick metal built especially for the design of low loss inductors. The filter has a center frequency of 51 GHz and 3dB bandwidth of 9 GHz, with a fractional bandwidth of 17.6% and a loaded Q of 5.6. The chip area of the filter is 160 μm × 135 μm excluding the pads. Since the proposed filter implementation does not require MIM processing, significant process cost savings can be achieved when compared to existing lumped filter implementations.
High density solenoidal series pair symmetric inductors and transformers
A high density symmetric inductor using a novel combination of solenoidal wound series stacked spirals is proposed in this paper. Series stacking in the individual sections increases overall inductance density, while solenoidal winding pushes the quality factors (Q) to higher frequencies. The proposed inductor achieves more than 65% improvement in peak-Q value and 100% higher peak-Q frequency and self resonance frequency, while occupying 20% lesser area when compared with a standard symmetric inductor with crossovers. Implemented in a high resistivity 0.18 μm CMOS silicon-on-insulator process with dual-thick metal stack, the proposed inductor achieves 70-nH inductance and a Q of 11.3 operating at 1.6 GHz within 250 × 250 μm2 area. This translates to a record figure-of-merit of 12.2, which is highest in air core symmetric inductor literature. Further, the proposed inductor configuration is extended to realize a planar transformer with very high turns ratio of 9.25 using only two metals. © 1963-2012 IEEE.
Design of novel high-Q multipath parallel-stacked inductor
In this brief, we present a novel multipath parallel-stacked inductor structure that significantly reduces the current crowding effects. Both the metal layers of the parallel stack are divided into multiple segments and crossovers are provided midway of each turn to steer the current in such a way that all its segments have equal path lengths. Following the multipath architecture, prototype inductor structures are fabricated in a 0.18-μm high-resistivity silicon-on-insulator technology using a dual thick metal stack process. Measurements show >30% improvement in quality factor (Q) with the proposed architecture when compared with a standard parallel-stacked inductor. The Q improvement achieved by the proposed inductor structure is shown to increase with the spiral thickness making them suitable for both radio frequency circuits and DC-DC buck converters without having to use magnetic materials. Via resistance is shown to limit the Q improvement possible with proposed inductor configuration.
High-Q characteristics of variable width inductors with reverse excitation
This brief proposes a technique to increase the performance of spiral inductors through appropriate selection of excitation port, especially in the case of variable width spirals. In this brief, forward excitation refers to applying ac voltage at the outer or upper terminal of the inductor with the inner or lower terminal grounded, while in reverse excitation, the inner or lower terminal is connected to the signal. Performance improvement with reverse excitation is explained using the voltage profile of the spiral. While tapered layout increased the peak-Q from 15.9 to 22.8, reverse excitation increased it further to 26.7. Moreover, reverse excitation also resulted in an increased peak-Q frequency from 5 to 8 GHz and self resonant frequency from 12 to 14.6 GHz in these tapered inductors. On the other hand, a similar approach is shown to be detrimental in the case of series stacked inductors, while symmetric inductors remain unaffected. © 2014 IEEE.
Integrated layout optimized high-g inductors on high-resistivity SOI substrates for RF front-end modules
This paper describes the effect of substrate resistivity on the performance characteristics of on-chip spiral inductors with an emphasis on high-resistivity (HR) silicon-on-insulator (SOI) substrates. The inductor characteristics are modeled using a physics based broadband and scalable compact model. Measurements show improvements up to 25% in quality factor (Q) characteristics of inductors on HR SOI substrate compared to those on a standard low resistivity bulk CMOS substrates. Electro-magnetic simulations demonstrate that similar Q improvement cannot be achieved by further increasing the substrate resistivity or by using patterned ground shield (PGS) beneath the inductor. Moreover, using a PGS is shown to be detrimental to inductor performance with a HR SOI substrate. With no further improvement in inductor Q possile with substrate engineering, minimizing the losses within the spiral through layout optimization becomes indispensable for improved performance. One such technique, that involves tapered spirals is shown to further increase the inductor Q by 20% over and above that is obtained with HR SOI.