Anjan Chakravorty

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This article presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3-D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations.

An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.

In this paper, we propose an efficient model for dynamic self-heating and thermal coupling in a multifinger transistor system. Essentially, the proposed model is an improvement over a state-of-the-art existing model from the viewpoint of simulation time. Verilog-A implementation of the proposed model does not require to use any voltage controlled voltage source. In a multifinger transistor system, with $n$ emitter fingers, our model uses $3n$ extra nodes in Verilog-A implementation whereas it is $2n^{2}-n$ for the state-of-the-art model. Note that our model requires no extra nodes for implementing the thermal coupling effects. We present that the transient simulation results of our model are identical with those of the state-of-the-art model. Electrothermal simulation using the proposed thermal model shows good agreement with the measured data. It is found that the proposed model simulates more than 40% faster compared with the existing model for a ring oscillator circuit.

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon-germanium HBTs fabricated in the STMicroelectronics B9MW technology.

A computationally efficient model for static self-heating and thermal coupling in a multi-finger bipolar transistor is proposed. Compared to an existing state-of-the-art model, our model differs only in the implementation strategy keeping the physical basis intact. The formulated model is implemented in Verilog-A without using any voltage controlled voltage sources. Temperature dependence of the thermal resistances are considered within the framework of the model. The number of extra nodes in our model reduces to 2n from n2 required in the state-of-the-art model with n as the number of emitter fingers in a transistor. The simulation results of our model are found to be identical with those of the state-of-the-art model demonstrating the capability of accurately considering the static self-heating and thermal coupling in a simple way. The model is found to accurately predict the measured data of a five-finger transistor. It is found that in high current operating regimes, our five finger transistor model simulates around 11% faster compared with the state-of-the-art model.

In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries.

An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.

In this work, we present a simple analytical model for electrothermal heating in multifinger bipolar transistors under realistic operating condition where all fingers are heating simultaneously. The proposed model intuitively incorporates the effect of thermal coupling among the neighboring fingers in the framework of self-heating bringing down the overall model complexity. Compared to the traditional thermal modeling approach for an n-finger transistor where the number of circuit nodes increases as n2, our model requires only n-number of nodes. The proposed model is scalable for any number of fingers and with different emitter geometries. The model is validated with 3-D thermal simulations and measured data from STMicroelectronics B4T technology. The Verilog-A implemented model simulates 40% faster than the conventional model in a transient simulation of a five-finger transistor.