Aniruddhan S

A comprehensive top-down system design methodology is presented and supported with a design of a Front-End Module (FEM) for 5G mobile applications targeting 24GHz-29GHz. While adopting package and PCB floor-planning and thermal challenges early in the design, a link budget analysis of a FEM in a system simulator followed by an implementation in GlobalFoundries' 22nm FDSOI process is reported with a focus on novel architectures to address system constraints. The FEM shows an excellent correlation between simulations and measurements and is further characterized post silicon by applying actual 5G signals in a real-time measurement mimicked simulation environment. A unified environment for co-designing and analysing the IC and package system is also described.

Two 28GHz mm-wave quadrature voltage-controlled oscillator designs in a 45nm bulk CMOS process are reported in this work. The first topology uses two VCOs coupled with each other using cascode devices. The second topology uses a single VCO followed by a Lange Coupler to give quadrature phase outputs. This comparative study shows that the latter exhibits better phase noise and tuning range with respect to the former. Post-layout EM simulations of the Lange Coupler QVCO predict an improvement of 4-6 dB in phase noise over the Cascode Injected QVCO, across all bit configurations. The total dc power consumption of this Lange coupled QVCO with two buffers is 20 mW when running at a power supply of 1.1V.

A comprehensive 5G system design methodology targeting 1Gbits/s next generation cellular communication is presented with associated design trade-offs. With an emphasis on beamforming to overcome mm-wave propagation challenges, a systematic link budget analysis has been carried out from 3GPP 5G NR standards to derive individual specifications for an RF front end module and RFIC. A detailed analysis of the effect of non-idealities on key figure of merits for receive and transmit chains is presented. Practical beamforming simulations is performed using a 2X4 dual polarized patch antenna array. It is also demonstrated that floorplan, power and thermal requirements play an important role in terms of decisions on technology-nodes, package-substrate selection and heterogenous integration.

This paper presents a quadrature 27-29GHz mmwave Integer-N phase locked loop (PLL) with an input reference frequency of 25MHz in a bulk CMOS 45nm technology. The PLL utilizes a Cascode Injection based Quadrature Voltage Controlled Oscillator (VCO) with a low phase noise of -87dBc/Hz@1MHz offset, and a 1024-2046 modular divider in step of 2. The PLL achieves a normalized phase noise of -90dBc/Hz at an offset of 1MHz even at a very high divide ratio of 1120 while consuming power of 65mW from a 1.1V power supply in post layout EM simulations. The jitter-power figure of merit (FOM) is -231dBc/Hz which is at par with state of the art PLL designs for 5G applications.

A passive eight-way power combined 28GHz mm-wave Gilbert cell I-Q Mixer in a 45nm bulk CMOS process is reported in this work for 5G RF beamformers. The 8:1 novel lumped quarter wave combiner/splitter utilizes transformer coupling to achieve a post layout efficiency of 67%, with a 2X reduction in area when compared to a spiral inductor-only implementation. With an isolation between ports greater than -22 dB, the amplitude and phase mismatch of the power combiner are kept within 0.3dB and 3 degrees respectively. Post-layout EM simulations of the I-Q mixer utilizing a current bleed technique predict a gain of 9dB, an OIP3 of +9dBm and a noise Figure of 9.9dB at a power consumption of 17mW in an active area of only 0.39mm2. The I-Q mismatch of the receiver is 0.5 dB in amplitude and 0.5 degree in phase, leading to an RSB \lt -40dBc. To ensure compact realization, two key layout improvements over a conventional mm-wave Gilbert cell are also discussed.

A 1.3 GHz bandwidth 4th order analog filter in a 45nm bulk CMOS process is reported in this work. The filter is a cascade of two Rauch bi-quads. The operational amplifiers for these biquad cells are based on an unique combination of both feedforward and miller compensation to achieve a high unity gain bandwidth of 4.5GHz, a high dc gain of 45dB and a good phase margin of 75 degrees. Post-layout simulations of the filter shows a 3dB cut off frequency of 1.3GHz with an IIP3 of + 12dBm and a total in band integrated noise voltage of 660μVRMS. The total dc power consumption of this filter is 24 mW at a 1.1V power supply.

An 8-way power combined, high gain, very low power varactor-less front end in a 45 nm bulk CMOS process is presented in this brief. The fully digital near-360° seven-bit reflection type phase shifter (RTPS) utilises a novel varactor-less tuning network in a triple resonating load along with negative resistance generators to reduce the insertion loss. A two-stage passive gm boosted CG-CS low noise amplifier (LNA) with series peaking delivers 32dB gain with a very low DC power consumption. The 8:1 lumped quarter wave combiner/splitter utilizes transformer coupling to achieve a post layout efficiency of 67%, with a 2X reduction in area when compared to a spiral inductor-only implementation. Post-layout EM simulations on the RTPS predict a 340° phase shift with insertion loss of 9± 5dB at a very high resolution of 2.8°. The front end yields an overall gain of 21± 5dB, with a worst-case noise figure (NF) of 4.7dB while consuming only 10mW per channel. With an inter channel isolation greater than 22 dB, the amplitude and phase mismatch of the front end are kept within 0.3dB and 3° respectively. The impact of module and PCB non-idealities on the beamformer performance have also been highlighted with support from initial system level simulations. To the best of the authors' knowledge, this is the first implementation of a fully digital near-360° RF beamforming front end with simultaneous high gain and phase resolution.

A comprehensive 5G top down system design methodology targeting a 200m link for the Local Multi Point Distribution Service (LMDS) band 27.5GHz-28.35GHz is presented and supported with a complete design of a beamforming receiver for handset applications. Adopting a top down approach, including package and PCB floor-planning and thermal challenges at an early stage of the design cycle, a link budget analysis has been carried out to derive detailed specifications for the beamformer and subsequently implemented in a generic CMOS 45nm process. In addition, a 2×4 dual polarized co-axial fed patch antenna array is designed with a gain of 14dBi and a bandwidth of 1 GHz. Some of the key tradeoffs while selecting novel circuit topologies in a top down approach have also been discussed. The impact of module and PCB non-idealities on the beamformer performance have also been highlighted with support from initial system level simulations.