IMPROVING FFT EFFICIENCY IN HIGH SPEED APPLICATIONS.

Fast Fourier Transform (FFT) processor based on pipeline architecture is found to be optimum for high speed real-time Digital Signal Processing (DSP) applications from the view points of speed and hardware complexity. Algorithms based on higher radices are helpful in stretching its speed limit. But the rate of growth in the complexity of hardware with increasing radix is disproportionately excessive. The impact of hardware complexity on algorithm implementation is inordinately pronounced for large values of data block length N. This paper presents methods that reduce the amount of hardware in high speed FFT processors and make them more efficient. It is shown that, for a radix-r processor, it results in the reduction of control circuit hardware by a factor of log//rN.