Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator without Reset

Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states. The first is adapted from a method used with a discrete-time delta-sigma modulator. It uses a sample-and-hold (S/H) at the Nyquist rate before the modulator and an adaptive equalizer at the Nyquist rate after the modulator for flattening the equivalent frequency response and eliminate memory. The newly proposed π-shifted filter, instead of flattening the equivalent discrete-time frequency response, merely ensures that the equivalent frequency response is symmetric about ω =π/2. In the time domain, this means that the equivalent impulse response at the Nyquist rate has zero-valued odd samples ensuring no cross-talk between two multiplexed inputs. Compared to the adaptive equalizer used for flattening the frequency response, this filter consumes three times lower power while occupying half the area. A two-channel ADC is demonstrated using both the adaptive equalizer the π-shifted filter. The ADC uses a CTDSM running at 6.144 MHz with an oversampling ratio (OSR) of 64, yielding a per-channel bandwidth of 24 kHz. The prototype in 180nm achieves a peak SNR/SNDR/DR of 91.7 dB/84.9 dB/98 dB and consumes 1.33mW per channel with adaptive equalizer. The SNR/SNDR/DR is 90.5 dB/83.7 dB/97 dB with a power consumption of 0.86mW per channel with the π-shifted filter.