A Low Power Multi-channel Input Delta-Sigma ADC without Reset

Memoryless delta-sigma ADCs can be implemented without resetting the modulator or decimation filter states using a modulator with unity STF, a Nyquist decimation filter and a front-end sample-and-hold. A previous implementation used a separate active sample-and-hold circuit using an opamp which contributed significantly to the power consumption, noise and distortion of the ADC. A passive alternative which eliminates all these shortcomings is proposed in this work. It is based on replicating the input capacitor of the delta-sigma modulator, sampling the input on all of them, and discharging them successively into the first integrator of the modulator. This technique is demonstrated with a 2 channel prototype simulated in a 180nm CMOS process. The prototype uses a 3rd order CIFF loop filter and a 4-bit quantizer, operates at 64 MHz, and has a per-channel bandwidth of 500 kHz. It consumes 20mA from a 1.8V supply, which is only 60% of the power consumed by a comparable system with a dedicated active sample-and-hold. The maximum SNR is 85 dB and the inter-channel crosstalk, limited by capacitor mismatch is 96 dB.