Efficient implementation of IEEE double precision floating-point multiplier on FPGA

An efficient architecture for implementation of double precision floating point multiplication on Field Programmable Gate Array (FPGA) is presented, based on the use of partial block multipliers. The proposed module gives excellent performance with efficient use of resources, achieving upto 292 MHz on a Xilinx Virtex II Pro device and 325 MHz on a Xilinx Virtex IV. The cost of the design is an error when compared to the IEEE standard, of up to 1 unit in last place (ulp) when used with partial nearest value rounding, or up to 2 ulp without rounding. Comparisons against the best reported multipliers in the literature show that the proposed module can outperform them. © 2008 IEEE.