A power optimized continuous-time ΔΣ ADC for audio applications

We present design considerations for low-power continuous-time ΔΣ modulators. Circuit design details and measurement results for a 15 bit audio modulator are given. The converter, designed in a 0.18 μm CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 μW from a 1.8 V supply. It features a third-order active-RC loop filter, a very low-power 4-bit flash quantizer, and an efficient excess-delay compensation scheme to reduce power dissipation. © 2008 IEEE.