Anjan Chakravorty

In this part, we propose a step-by-step strategy to model the static thermal coupling factors between the fingers in a silicon based multifinger bipolar transistor structure. First we provide a physics-based formulation to find out the coupling factors in a multifinger structure having no-trench isolation (cij,nt). As a second step, using the value of cij,nt, we propose a formulation to estimate the coupling factor in a multifinger structure having only shallow trench isolations (cij,st). Finally, the coupling factor model for a deep and shallow trench isolated multifinger device (cij,dt) is presented. The proposed modeling technique takes as inputs the dimensions of emitter fingers, shallow and deep trench isolations, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are validated against 3D TCAD simulations of multifinger bipolar transistors with and without trench isolations. Geometry scalability of the model is also demonstrated.

In this brief, we propose a step-by-step strategy to accurately estimate the finger temperature in a silicon-based multifinger bipolar transistor structure from conventional measurements. First we extract the nearly zero-power self-heating resistances (Rth,ii (Ta)) and thermal coupling factors (cij (Ta)) at a given ambient temperature. Now, by applying the superposition principle on these variables at nearly zero-power, where the linearity of the heat diffusion equation is preserved, we estimate an effective thermal resistance (Rth,i (Ta)) and the corresponding revised finger temperature Ti (Ta). Finally, the Kirchhoff's transformation on Ti (Ta) yields the true temperature at each finger (Ti (Ta,Pd)). The proposed extraction technique automatically includes the effects of back-end-of-line metal layers and different types of trenches present within the transistor structure. The technique is first validated against 3-D TCAD simulation results of bipolar transistors with different emitter dimensions and then applied on actual measured data obtained from the state-of-the-art multifinger SiGe HBT from STMicroelectronics B5T technology. It is observed that the superposition of raw measured data at around 40 mW power underestimates the true finger temperature by around 10%.

In this paper, we have assessed the RF measurements of SiGe HBTs upto 500 GHz using TCAD simulation for the first time. In order to bring confidence in simulation, the device geometries and doping profiles are captured in the simulation deck. Then all the basic DC and RF properties are calibrated with the measured data for two different geometries. Additionally the simulated unilateral gain and small signal current gain are also brought in agreement with the corresponding measured data at different bias voltages for both the devices. Finally bias and frequency dependent S- parameter measurements are compared with the TCAD simulation and resulting issues are discussed.

Terahertz (THz) silicon-based electronics is undergoing rapid developments. In order to keep this momentum high, an accurate and optimized on-wafer characterization procedure needs to be developed. While evaluating passive elements, the measured s-parameter data can be verified by a direct use of EM simulation tools. However, this verification requires to precisely introduce part of the measurement environment such as the probes, pads, and access lines to accurately predict the impact of calibration and layout for on-wafer measurements. Unfortunately, this procedure is limited to passive elements. Hence, in this work, we propose a new procedure to emulate the measurement of active devices using an electromagnetic SPICE cosimulation. By this method, one can clearly highlight that a measurement artifact that was observed for the transistor measurement can be reproduced. One of the most representative examples of measurement artifact involves the measurement and estimation of ${f}_{\text {MAX}}$ which is not constant over all frequency bands. Also, the measurement is difficult to perform above 40 GHz. This typical problem is now undoubtedly attributed to the probe-to-substrate coupling and probe-to-probe coupling which are strongly dependent on the probe geometry. Finally, this cosimulation procedure evidently underlines the need for an optimized deembedding procedure above 200 GHz.

The undesired behavior of the substrate significantly affects the output impedance of the device; hence degrades circuit performance mainly in the high frequency regime. Therefore, for high-speed and RF circuits, collector-substrate modeling has to be sufficiently accurate. In this paper, an improved collector-substrate equivalent circuit model is proposed. The circuit model elements are physics based and are calculated from technological data. The validity of the equivalent circuit has been verified by on-wafer measurements of an SiGe HBT fabricated in B55 technology up to 330 GHz, the highest frequency reported so far for collector-substrate modeling. The proposed substrate network can be considered as an extension of the latest large-signal HICUM model (L2v2.4).

This paper proposes a novel 3D nanowire (NW) based SiGe HBT for the first time. The overall purpose is to estimate the RF performance of an NW device based on the state-of-the-art B55 technology from STMicroelectronics. The challenges associated with the device fabrication and corresponding solutions are briefed. The proposed NW-HBT array predicts an fMAX(> 900GHz) that is more than twice of that obtainable from the corresponding bulk SiGe HBT.

From the perspectives of characterized data, calibrated TCAD simulations and compact modeling, we present a deeper investigation of the very high frequency behavior of state-of-the-art sub-THz silicon germanium heterojunction bipolar transistors (SiGe HBTs) fabricated with 55-nm BiC-MOS process technology from STMicroelectronics. The TCAD simulation platform is appropriately calibrated with the measurements in order to aid the extraction of a few selected high-frequency (HF) parameters of the state-of-the-art compact model HICUM, which are otherwise difficult to extract from traditionally prepared test-structures. Physics-based strategies of extracting the HF parameters are elaborately presented followed by a sensitivity study to see the effects of the variations of HF parameters on certain frequency-dependent characteristics until 500 GHz. Finally, the deployed HICUM model is evaluated against the measured s-parameters of the investigated SiGe HBT until 500 GHz.

In this paper, we extend the model developed in part-I of this work to include the effects of the back-end-of-line (BEOL) metal layers and test its validity against on-wafer measurement results of SiGe heterojunction bipolar transistors (HBTs). First we modify the position dependent substrate temperature model of part-I by introducing a parameter to account for the upward heat flow through BEOL. Accordingly the coupling coefficient models for bipolar transistors with and without trench isolations are updated. The resulting modeling approach takes as inputs the dimensions of emitter fingers, shallow and deep trench isolation, their relative locations and the temperature dependent material thermal conductivity. Coupling coefficients obtained from the model are first validated against 3D TCAD simulations including the effect of BEOL followed by validation against measured data obtained from state-of-art multifinger SiGe HBTs of different emitter geometries.

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This article presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3-D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations.

An efficient technique to extract the front-end-of-line and back-end-of-line components of the thermal resistance in bipolar transistors is proposed. The proposed approach is tested with the numerical simulations of silicon germanium HBTs corresponding to the STMicroelectronics B9MW process. We also predict the overestimate in the conventional thermal resistance models which neglects the thermal resistance contribution from the back-end-of-line. The results of the proposed extraction technique are observed to be in agreement with the numerical simulations for different emitter geometries.